Classical linear amplifiers, like Class-A, Class-B or Class-AB amplifiers, are known to be quite inefficient. Class-D amplifiers have power-efficiency advantages over these linear amplifier classes. In linear amplifiers such as Class-AB amplifiers significant amounts of power are lost due to biasing elements and the linear operation of the output transistors. Because the transistors of a Class-D amplifier are simply used as switches to steer current through the load, minimal power is lost due to the output stage. Most power lost in an amplifier is dissipated as heat. Because heat sink requirements can be greatly reduced or eliminated in Class-D amplifiers, they are ideal for compact high-power applications and become increasingly important.
While there are a variety of modulator topologies used in modern Class-D amplifiers, the most basic topology utilizes pulse-width modulation (PWM) with a triangle-wave (or sawtooth) oscillator signal. A simplified PWM-based, half-bridge Class-D amplifier consists of a pulse-width modulator, two output metal oxide semiconductor field-effect transistors (MOSFETs), and an external lowpass filter to recover the amplified signal, like an amplified audio signal. The two MOSFETS, e.g. one p-channel and one n-channel MOSFET, operate as current-steering switches by alternately connecting the output node to a supply voltage and ground. In order to extract the amplified (audio) signal from this PWM waveform, the output of the Class-D amplifier is fed to a lowpass filter. Because the output transistors switch the output to either the supply voltage or ground, the resulting output of a Class-D amplifier is a high-frequency square wave. The switching frequency for most Class-D amplifiers is typically between 250 kHz to 1.5 MHz.
In Class-D amplifiers, the switches are either fully on or fully off, significantly reducing the power losses in the output devices. Efficiencies of 90-95% are possible.
The input signal, e.g. an audio input signal, is used to modulate a PWM carrier signal which drives the output devices, with the last stage being the lowpass filter to remove the high frequency PWM carrier frequency.
The output square wave is pulse-width modulated by the input, e.g. the audio input signal. PWM is accomplished by comparing the (audio) input signal to an internally generated triangle-wave (or sawtooth) oscillator signal. The resulting duty cycle of the square wave is proportional to the level of the input signal. When no input signal is present, the duty cycle of the output waveform is equal to 50%. In other words, the (audio) input signal can be represented by a square wave with only two possible levels (“high” and “low”). The PWM square wave has a fixed frequency, but the time it is in the “high” and “low” states is not always 50%. It rather varies following the incoming signal. In this way, when the input signal increases, the “high” state will be present for longer than the “low” state, i.e. the value of the duty cycle increases (to is become larger than 50%). When the input signal decreases, the “low” state will be present for longer than the “high” state”, i.e. the value of the duty cycle decreases (to become lower than 50%). From these values of the duty cycles, the input signal can be restored.
That is, a digital Class-D amplifier is a circuit based on a PWM technique which translates the amplitude of a given input sample into a duty cycle of a high frequency reference signal. This high frequency signal directly drives the output buffer that, in the simplest possible implementation, could be a pure inverter. Class-D amplifiers take on many different forms, some can have digital inputs and some can have analog inputs.
FIG. 1a shows a simplified block diagram of a digital Class-D amplifier 10 with differential outputs PWM modulation, that is commonly used in the industry, where the input signal INPUT is compared with a triangular reference waveform. For this purpose, the input signal is compared with positive cycles of the reference signal REFERENCE_P and with negative cycles of the reference signal REFERENCE_N. The modulation scheme shown in FIG. 1a is called “quaternary modulation”, since all four digital states combinations “00”, “01”, “10”, “11” could appear at the outputs at each time instant, i.e. the output signals PWM_P and PWM_N can both be “high” (state “11”), both be “low” (state “00”) or one can be “high” and the other can be “low” (states “10” or “01”). The resulting difference signal PWM_DIFF resulting from the output signals PWM_P and PWM_N is also given in FIG. 1a. 
FIG. 1b illustrates a resulting PWM output waveform when an analog audio signal is compared with a triangular reference waveform. As can be seen from FIG. 1b, the output waveform is pulse-width modulated due to the varying input-signal level.
Another kind of modulation, named “ternary modulation”, can be obtained by applying some logic equations to the quaternary outputs. More precisely, the ternary signals can be obtained by using the following equations:PWM—P—TERN=(PWM—P—QUAT and not PWM—N—QUAT)  (1)PWM—N—TERN=(PWM—N—QUAT and not PWM—P—QUAT)  (2)
In ternary modulation, only three states can appear at the two outputs, i.e. “00”, “01” and “10”, i.e. the ternary output signals PWM_P_TERN and PWM_N_TERN can not be “high” at the same time. FIG. 2 shows these waveforms. The waveform named PWM_DIFF represents the differential behaviour of the Class-D outputs in case of ternary modulation.
It can be noticed that during positive cycles of the input waveforms only PWM_P_TERN is active, i.e. different from zero, while during negative cycles only PWM_N_TERN is active.
Ternary modulation is usually preferred to quaternary one because of the much lower “common mode” Electromagnetic Interference (EMI) pollution.
One problem typical of the ternary modulation is the so called “minimum pulse width”, shown in the difference waveform PWM_DIFF in FIG. 2, which happens for input signal levels approaching zero, due to rise and fall times of the output waveforms. This behavior is responsible for a significant non-linearity error since the small signals effective pulse amplitude is corrupted by the non-ideal rising and falling edges.
A ternary modulation scheme is weaker than a quaternary one regarding the mismatch on rising and/or falling times of one single ended output versus the other. In other words, a pure ternary scheme shows rather high harmonics distortion values whenever the rising (falling) time of the PWM_P waveform is different from the rising (falling) time of the PWM_N waveform. Edges mismatch between the two outputs PWM_P and PWM_N can arise for various reasons, such as different internal signal path lengths, different output loads, different signal paths on the board etc. Various techniques have been developed to compensate those non-idealities. For instance, U.S. Pat. No. 6,614,297 and U.S. Pat. No. 5,617,058 describe two different ways to cope with this problem. However, the mechanisms described in U.S. Pat. No. 6,614,297 and U.S. Pat. No. 5,617,058 do not solve this problem.
The mechanism described in U.S. Pat. No. 6,614,297, shown in FIG. 3a, generates a minimum pulse by shifting one of the two outputs and then applying the ternary logic equations (1) and (2) as set forth above. For low levels near zero extra pulses are generated, while as soon as the signal increases such pulses decrease in width, till they disappear. In this way the ternary modulation problem for very low levels is simply translated from the zero input level range to a level which depends on the amount of shift implemented.
The mechanism described in U.S. Pat. No. 5,617,058, shown in FIG. 3b, tries to face the minimum pulse distortion by adding compensating pulses for low level signals, meantime enlarging the signal pulse by the same width as the compensating pulse. The mechanism described in U.S. Pat. No. 5,617,058 doubles non symmetrical shift and increases the distortion due to the non-symmetric relative shift of the positive and negative cycles.